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AD73522 a rev. prc 05/99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p .o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1998 dual analog front end with flash based dsp microcomputer preliminary technical data preliminary technical data features afe performance two 16-bit a/d converters 78 db adc snr two 16-bit d/a converters 77 db dac snr programmable input/output sample rates 64 ks/s maximum sample rate programmable input/output gain on-chip reference dsp performance 19 ns instruction cycle time @ 3.3 volts, 52 mips sustained performance AD73522-80 80k bytes of on-chip ram, configured as 16k words program memory ram and 16k words data memory ram AD73522-40 40k bytes of on-chip ram, configured as 8k words program memory ram and 8k words data memory ram flash memory 64 kbytes writable in pages of 128 bytes fast page write cycle of 5 ms (typical) general description the AD73522 is a single-device incorporating a dual analog front end, microcomputer optimized for digital signal processing (dsp) and a flash based boot memory for the dsp. the AD73522s analog front end (afe) section features a dual front-end converter for general purpose applications including speech and telephony. the afe section features two 16-bit a/d conversion channels and two 16-bit d/a conversion channels. each channel provides 77 db signal-to- noise ratio over a voiceband signal bandwidth. it also features an input to output gain network in both the analog and digital domains. this is featured on both codecs and can be used for impedance matching or scaling when interfacing to subscriber line interface circuits (slics) the AD73522 is particularly suitable for a variety of applica- tions in the speech and telephony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. the low group delay characteristic of the afe makes it suitable for single or multichannel active control applications. the a/d and d/a conversion channels feature functional block diagram serial ports sport 1 sport 0 byte dma controller external data bus external address bus full memory mode memory programmable i/o and flags 16k pm (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data 16k dm (optional 8k) serial port ref adc1 adc2 dac1 dac2 analog front end section sport 2 flash byte memory 64 kbytes programmable input/ouput gains with ranges 38 db and 21 db respectively. an on-chip reference voltage is included to allow single supply operation. the AD73522s dsp engine combines the adsp-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities and on-chip program and data memory. the AD73522-80 integrates 80k bytes of on-chip memory configured as 16k words (24-bit) of program ram, and 16k words (16-bit) of data ram. the AD73522-40 integrates 40k bytes of on-chip memory configured as 8k words (24- bit) of program ram, and 8k words (16-bit) of data ram. both devices feature a flash memory array of 64 kbytes (512 kbits) connected to the dsps byte-wide dma port (bdma). this allows non-volatile storage of the dsps boot code and system data parameters. power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. the AD73522 is available in a 119-ball pbga package.
AD73522 C2C rev. prc 05/99 preliminary technical data preliminary technical data architecture overview the AD73522 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single processor cycle. the AD73522 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 byte dma controller external data bus external address bus full memory mode memory programmable i/o and flags 16k pm (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data 16k dm (optional 8k) serial port ref adc1 adc2 dac1 dac2 analog front end section sport 2 flash byte memory 64 kbytes figure 1. functional block diagram figure 1 is an overall block diagram of the AD73522. the processor section contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/ subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the AD73522 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off- chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the AD73522 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the AD73522 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). analog front end the afe section is configured as a separate block which is normally connected to either sport0 or sport1 of the dsp section. as it is not hard-wired to either sport the user has total flexibility in how they wish to allocate system resources to support the afe. it is also possible to further expand the number of analog i/o channels connected to the sport by cascading other single or dual channel afes (ad73311 or ad73322) external to the AD73522. the afe is configured as a cascade of two i/o channels (similar to that of the discrete ad73322 - refer to the ad73322 datasheet for more details) with each channel having a separate 16-bit sigma-delta based adc and dac. both channels share a common reference whose nominal value is 1.2v. figure 2 shows a block diagram of the afe section of the AD73522. it shows two channels of adc and dac conversion alog with a common reference. communication to both channels is handled by the sport2 block which interfaces to either sport0 or sport1 of the dsp section. figure 3 shows the analog connectivity available on each channel of the afe (channel 1 is detailed here). both channels feature fully differential inputs and outputs. the
AD73522 C3C rev. prc 05/99 preliminary technical data preliminary technical data input section allows direct connection to the internal programmable gain amplifier at the input of the sigma-delta adc section or optional inverting amplifiers may be configured to provide some fixed external gain or to interface to a transducer with relatively high source impedance. the input section also features programmable differential channel inversion and configuration of the the differential input as two separate single-ended inputs. the adc features a second order sigma-delta modulator which samples at mclk/8. its bitstream output is filtered and decimated by a sinc-cubed decimator to provide a sample rate selectable from 64 khz, 32 khz, 16 khz or 8 khz (based on an mclk of 16.384 mhz). the dac channel features a sinc-cubed interpolator which increases the sample rate from the selected rate to the digital sigma-delta modulator rate of mclk/8. the digital sigma- delta modulators output bit-stream is fed to a single-bit dac whose output is reconstructed/filtered by two stages of low- pass filtering (switched capacitor and continuous time) before being applied to the differential output driver. each channel also features two programmable gain elements, analog gain tap (agt) and digital gain tap (dgt), which, when enabled, add a signed and scaled amount of the input signal to the dacs output signal. this is of particular use in line impedance balancing when interfacing the afe to subscriber line interface circuits (slics). vinn1 vinp1 vfbn1 vfbp1 v ref voutp1 voutn1 continuous time low-pass filter +6/-15db pga v ref analog loopback select single-ended enable invert inverting op- amps analog gain tap gain +/- 1 0/38 db pga refout refcap reference figure 3: analog front end configuration + + vinn1 vinp1 vfbn1 vfbp 1 v ref analog sigma-delta modulator - + 0/38db pga voutp1 voutn1 continuous time low-pass filter +6/-15db pga + switched- capacitor low pass filter interpolator digital sigma-delta modulator 1-bit dac + gain +/- 1 - + + - - gain +/- 1 decimator sdi sdifs sclk2 seria l i/o port refcap refout reference se resetc sdofs sdo mclk + + vinn2 vinp2 vfbn2 vfbp2 v ref analog sigma-delta modulator - + 0/38db pga voutp2 voutn2 continuous time low-pass filter +6/-15db pga + switched- capacitor low pass filter interpolator digital sigma-delta modulator 1-bit dac + + - - gain +/- 1 decimator + gain +/- 1 - invert single-ended enable analog loop back invert single-ended enable analog loop back figure 2: functional block diagram of analog front end section
C4C rev. prc 05/99 AD73522Cspecifications preliminary technical data (avdd = dvdd = +3.0v to 3.6v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted) parameter min typ max units test conditions afe section reference refcap absolute voltage, v refcap 1.08 1.2 1.32 v refcap tc 50 ppm/c 0.1 f capacitor required from refout refcap to agnd2 typical output impedance 130 w absolute voltage, v refout 1.08 1.2 1.32 v unloaded minimum load resistance 1 kw maximum load capacitance 100 pf input amplifier offset 1.0 mv maximum output swing 1.578 v max. output swing =(1.578/1.2)*v refcap feedback resistance 50 kw f c = 32 khz feedback capacitance 100 pf analog gain tap gain at max. setting +1 gain at min. setting -1 gain resolution 5 bits gain step size = 0.0625 gain accuracy 1.0 % output unloaded settling time 1.0 ms tap gain change of -fs to +fs delay 0.5 ms adc specifications maximum input range at vin 2, 3 1.578 v p-p measured differentially. C2.85 dbm max. input = (1.578/1.2)*v refcap nominal reference level at vin 1.0954 v p-p measured differentially (0 dbm0) C6.02 dbm absolute gain pga = 0 db C0.5 0.4 +1.2 db 1.0 khz, 0 dbm0 pga = 38 db C1.5 C0.7 +0.1 db 1.0 khz, 0 dbm0 gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) refer to figure 5 pga = 0 db 72 78 db 300 hz to 3400 hz; f samp = 64 khz 78 db 300 hz to 3400 hz; f samp = 8 khz 55 57 db 0 hz to f samp /2; f samp = 64 khz pga = 38 db 52 56 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion pga = 0 db C84 C73 db 300 hz to 3400 hz; f samp = 64 khz pga = 38 db C70 C60 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C65 db pga = 0 db idle channel noise C71 dbm0 pga = 0 db crosstalk, adc-to-dac C100 db adc input level: 1.0khz, 0 dbm0 dac input at idle adc-to-adc -100 db adc1 input level: 1.0khz, 0 dbm0 adc2 input at idle. input amps bypassed -70 db input amplifiers included in input channel dc offset C30 +10 +45 mv pga = 0 db power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s input resistance at pga 2, 4, 6 20 kw dmclk = 16.384 mhz; input amplifiers bypassed and agt off digital gain tap gain at max. setting +1 gain at min. setting -1 gain resolution 16 bits tested to 5 msbs of settings delay 25 ms includes dac delay settling time 100 ms tap gain change from -fs to +fs; includes dac settling time
C5C rev. prc 05/99 AD73522 preliminary technical data preliminary technical data parameter min typ max units test conditions (style: table col.head) dac specifications maximum voltage output swing 2 single ended 1.578 v p-p pga = 6 db C2.85 dbm max. output = (1.578/1.2)*v refcap differential 3.156 v p-p pga = 6 db 3.17 dbm max. output = 2*((1.578/1.2)*v refcap ) nominal voltage output swing (0 dbm0) single-ended 1.0954 v p-p pga = 6 db C6.02 dbm differential 2.1909 v p-p pga = 6 db 0 dbm output bias voltage 1.2 v refout unloaded absolute gain C0.5 +0.4 +1.2 db 1.0 khz, 0 dbm0; unloaded gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) at 0 dbm0 refer to figure 6: av dd = 3.00v +/- 5% pga = 6 db 62.5 77 db 300 hz to 3400 hz; f samp = 64 khz total harmonic distortion at 0 dbm0 av dd = 3.00v +/- 5% pga = 6 db -80 C62.5 db 300 hz to 3400 hz; f samp = 64 khz intermodulation distortion C85 db pga = 0 db idle channel noise C85 dbm0 pga = 0 db crosstalk, dac-to-adc C90 db adc input level: agnd; dac output level: 1.0 khz, 0 dbm0; input amplifiers bypassed -77 db input amplifiers included in input channel dac-to-dac C100 db dac1output level:agnd; dac2 output level: 1.0 khz, 0 dbm0 power supply rejection C65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s interpolator bypassed 50 s output dc offset 2, 7 C20 +12 +45 mv minimum load resistance, r l 2, 8 single-ended 4 150 w differential 150 w maximum load capacitance, c l 2, 8 single-ended 4 500 pf differential 100 pf logic inputs v inh , input high voltage dvdd C 0.8 dvdd v v inl , input low voltage 0 0.8 v i ih , input current -10 +10 a c in , input capacitance 10 pf logic output v oh , output high voltage dvdd C 0.4 dvdd v |iout| - 100 a v ol , output low voltage 0 0.4 v |iout| - 100 a three-state leakage current C10 +10 a power supplies avdd1, avdd2 3.0 3.6 v dvdd 3.0 3.6 v i dd 10 see table i notes 1 operating temperature range is as follows: C20c to +85c. therefore, t min = C20c and t max = +85c. 2 test conditions: input pga set for 0 db gain, output pga set for 6 db gain, no load on analog outputs (unless otherwise noted). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sample rate and the external digital filtering. 6 the adcs input impedance is inversely proportional to dmclk and is approximated by: (3.3 * 10 11 )/dmclk. 7 between voutp1 and voutn1 or between voutp2 and voutn2. 8 at vout output. 9 frequency responses of adc and dac measured with input at audio reference level (the input level that produces an output level of C10 dbm0), with 38 db preamplifier bypassed and input gain of 0 db. 10 test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs. specifications subject to change without notice.
C6C rev. prc 05/99 AD73522Cspecifications preliminary technical data (avdd = dvdd = +3.0v to 3.6v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted) parameter test conditions min typ max unit dsp section v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 a i il lo-level input current 3 @ v dd = max v in = 0 v 10 a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 10 a i dd supply current (idle) 9 @ v dd = 3.3 t ck = 19 ns 10 10 ma t ck = 25 ns 10 8ma t ck = 30 ns 10 7ma i dd supply current (dynamic) 11 @ v dd = 3.3 t amb = +25c t ck = 19 ns 10 51 ma t ck = 25 ns 10 41 ma t ck = 30 ns 10 34 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf notes 1 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 1 2 input only pins: reset, br, dr0, dr1, pwd. 1 3 input only pins: clkin, reset, br, dr0, dr1, pwd. 1 4 output pins: bg, pms, dms, bms, ioms, cms, rd, wr, pwdack, a0, dt0, dt1, clkout, fl2C0, bgh. 1 5 although specified for ttl outputs, all AD73522 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 1 6 guaranteed but not tested. 1 7 three-statable pins: a0Ca13, d0Cd23, pms, dms, bms, ioms, cms, rd, wr, dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0Cpf7. 1 8 0 v on br. 1 9 idle refers to AD73522 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 applies to pbga package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice.
C7C rev. prc 05/99 AD73522 preliminary technical data preliminary technical data power consumption conditions typ. max. se mclk on test conditions afe section adcs on only 11.5 12 1 yes refout disabled dacs on only 20 22 1 yes refout disabled adcs and dacs on 24.5 27 1 yes refout disabled adcs and dacs 30 34 1 yes refout disabled and input amps on adcs and dacs 29 32.5 1 yes refout disabled and agt on all sections on 37 42 1 yes refcap on only 0.8 1.25 0 no refout disabled refcap and 3.5 4.5 0 no refout on only all afe sections off 1.5 1.8 0 yes mclk active levels equal to 0v and dvdd all afe sections off 10 a 40 a 0 no digital inputs static and equal to 0 v or dvdd flash section read mode 12 bms = rd = 0; wr = 1 write mode 15 bms = wr = 0; rd = 1 standby current 15 m a bms = rd = wr = 1 the above values are in ma and are typical values unless otherwise noted. timing characteristics - afe section parameter limit units description clock signals see figure 1 t 1 61 ns min 16.384 mhz mclk period t 2 24.4 ns min mclk width high t 3 24.4 ns min mclk width low serial port see figures 3 and 4 t 4 t 1 ns min sclk period (sclk = mclk) t 5 0.4 * t 1 ns min sclk width high t 6 0.4 * t 1 ns min sclk width low t 7 20 ns min sdi/sdifs setup before sclk low t 8 0 ns min sdi/sdifs hold after sclk low t 9 10 ns max sdofs delay from sclk high t 10 10 ns min sdofs hold after sclk high t 11 10 ns min sdo hold after sclk high t 12 10 ns max sdo delay from sclk high
AD73522 C8C rev. prc 05/99 preliminary technical data preliminary technical data a b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u 1234567 1234567 pbga ball configurations pbga ball pbga ball pbga ball pbga ball number name number name number name number name a1 irqe /pf4 e3 rfs0 j5 d22 n7 d13 a2 dms e4 a3/iad2 j6 d21 p1 ebr a3 vdd(int) e5 a2/iad1 j7 d20 p2 d0/iad13 a4 clkin e6 a1/iad0 k1 elout p3 dvdd a5 a11/iad10 e7 a0 k2 elin p4 dgnd a6 a7/iad6 f1 dr0 k3 eint p5 resetc a7 a4/iad3 f2 sclk0 k4 d19 p6 sclk2 b1 irql0 /pf5 f3 dt1 k5 d18 p7 mclk b2 pms f4 pwdack k6 d17 r1 sdo b3 wr f5 bgh k7 d16 r2 sdofs b4 xtal f6 pf0[mode a] l1 bg r3 sdifs b5 a12/iad11 f7 pf1[mode b] l2 d3/ iack r4 sdi b6 a8/iad7 g1 tfs1 l3 d5/ial r5 se b7 a5/iad4 g2 rfs1 l4 d8 r6 refcap c1 irql1 /pf6 g3 dr1 l5 d9 r7 refout c2 ioms g4 gnd l6 d12 t1 vfbp1 c3 rd g5 pwd l7 d15 t2 vinp1 c4 vdd(ext) g6 vdd(ext) m1 ebg t3 vfbn1 c5 a13/iad12 g7 pf2[mode c] m2 d2/iad15 t4 vinn1 c6 a9/iad8 h1 sclk1 m3 d4/ is t5 vfbn2 c7 gnd h2 ereset m4 d7/ iwr t6 vinn2 d1 irq2 /pf7 h3 reset m5 vdd(ext) t7 vfbp2 d2 cms h4 pf3 m6 d11 u1 agnd d3 bms h5 fl0 m7 d14 u2 avdd d4 clkout h6 fl1 n1 br u3 voutp2 d5 gnd h7 fl2 n2 d1/iad14 u4 voutn2 d6 a10/iad9 j1 ems n3 vdd(int) u5 voutp1 d7 a6/iad5 j2 ee n4 d6/ ird u6 voutn1 e1 dt0 j3 eclk n5 gnd u7 vinp2 e2 tfs0 j4 d23 n6 d10
AD73522 C9C rev. prc 05/99 preliminary technical data preliminary technical data ordering guide temperature package package model range description option AD73522-80 -20 c to +85 c 119-ball plastic ball grid array b-119 AD73522-40 -20 c to +85 c 119-ball plastic ball grid array b-119 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD73522 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD73522 C10C rev. prc 05/99 preliminary technical data preliminary technical data pin function description mnemonic function vinp1 analog input to the inverting terminal of the inverting input amplifier on channel 1's positive input. vfbp1 feedback connection from the output of the inverting amplifier on channel 1's positive input. when the input amplifiers are bypassed, this pin allows direct access to the positive input of channel 1's sigma delta modulator. vinn1 analog input to the inverting terminal of the inverting input amplifier on channel 1's negative input. vfbn1 feedback connection from the output of the inverting amplifier on channel 1's negative input. when the input amplifiers are bypassed, this pin allows direct access to the negative input of channel 1's sigma delta modulator. refout buffered reference output, which has a nominal value of 1.2 v. refcap a bypass capacitor to agnd2 of 0.1 f is required for the on-chip reference. the capacitor should be fixed to this pin. avdd2 analog power supply connection for codec 2. agnd2 analog ground/substrate connection for codec 2. dgnd digital ground/substrate connection. dvdd digital power supply connection. reset a ctive low reset signal. this input resets the entire chip, resetting the control registers and clearing the digital circuitry. sclk output serial clock whose rate determines the serial transfer rate to/from the codec. it is used to clock data or control information to and from the serial port (sport). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by an integer numberthis integer number being the product of the external master clock rate divider and the serial clock rate divider. mclk master clock input. mclk is driven from an external clock signal. sdo serial data output of the codec. both data and control information may be output on this pin and is clocked on the positive edge of sclk. sdo is in three-state when no information is being transmitted and when se is low. sdofs framing signal output for sdo serial transfers. the frame sync is one-bit wide and it is active one sclk period before the first bit (msb) of each output word. sdofs is referenced to the positive edge of sclk. sdofs is in three-state when se is low. sdifs framing signal input for sdi serial transfers. the frame sync is one-bit wide and it is valid one sclk period before the first bit (msb) of each input word. sdifs is sampled on the negative edge of sclk and is ignored when se is low. sdi serial data input of the codec. both data and control information may be input on this pin and are clocked on the negative edge of sclk. sdi is ignored when se is low. se sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport are three-stated and the input pins are ignored. sclk is also disabled internally in order to decrease power dissipation. when se is brought high, the control and data registers of the sport are at their original values (before se was brought low), however the timing counters and other internal registers are at their reset values. agnd1 analog ground/substrate connection for codec 1. avdd1 analog power supply connection for codec 1. voutp2 analog output from the positive terminal of output channel 2. voutn2 analog output from the negative terminal of output channel 2. voutp1 analog output from the positive terminal of output channel 1. voutn1 analog output from the negative terminal of output channel1. vinp2 analog input to the inverting terminal of the inverting input amplifier on channel 2's positive input. vfbp2 feedback connection from the output of the inverting amplifier on channel 2's positive input. when the input amplifiers are bypassed, this pin allows direct access to the positive input of channel 2's sigma delta modulator. vinn2 analog input to the inverting terminal of the inverting input amplifier on channel 2's negative input. vfbn2 feedback connection from the output of the inverting amplifier on channel 2's negative input. when the input amplifiers are bypassed, this pin allows direct access to the negative input of channel 2's sigma delta modulator. reset (input) processor reset input br (input) bus request input bg (output) bus grant output bgh (output) bus grant hung output dms (output) data memory select output pms (output) program memory select output ioms (output) memory select output bms (output) byte memory select output cms (output) combined memory select output rd (output) memory read enable output wr (output) memory write enable output
AD73522 C11C rev. prc 05/99 preliminary technical data preliminary technical data irq2/ (input) edge- or level-sensitive interrupt pf7 (input/output) request. 1 programmable i/o pin irql0/ (input) level-sensitive interrupt requests 1 pf6 (input/output) programmable i/o pin irql1/ ( input) level-sensitive interrupt requests 1 pf5 (input/output) programmable i/o pin irqe/ (input) edge-sensitive interrupt requests 1 pf4 (input/output) programmable i/o pin mode d/ (input) mode select inputchecked only during reset pf3 (input/output) programmable i/o pin during normal operation mode c/ (input) mode select inputchecked only during reset pf2 (input/output) programmable i/o pin during normal operation mode b/ (input) mode select inputchecked only during reset pf1 (input/output) programmable i/o pin during normal operation mode a/ (input) mode select inputchecked only during reset pf0 (input/output) programmable i/o pin during normal operation clkin, xtal (inputs) clock or quartz crystal input clkout (output) processor clock output sport0 (inputs/outputs) serial port i/o pins sport1 (inputs/outputs) serial port i/o pins irq1:0 (inputs) edge- or level-sensitive interrupts, fi (input) flag in 2 fo (output) flag out 2 pwd (input) power-down control input pwdack (output) power-down control output fl0, fl1, fl2 (outputs) output flags vdd and gnd power and ground ez-port (inputs/outputs) for emulation use
AD73522 C12C rev. prc 05/99 preliminary technical data preliminary technical data functional description - afe encoder channels both encoder channels consist of a pair of inverting op-amps with feedback connections which can be bypassed if required, a switched capacitor pga and a sigma-delta analog-to-digital converter (adc). an on-board digital filter, which forms part of the sigma-delta adc, also performs critical system-level filtering. due to the high level of oversampling, the input antialias requirements are reduced such that a simple single pole rc stage is sufficient to give adequate attenuation in the band of interest. programmable gain amplifier each encoder sections analog front end comprises a switched capacitor pga which also forms part of the sigma-delta modulator. the sc sampling frequency is dmclk/8. the pga, whose programmable gain settings are shown in table i, may be used to increase the signal level applied to the adc from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. the input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. the pga gain is set by bits igs0, igs1 and igs2 (crd:0C 2) in control register d. table i. pga settings for the encoder channel igs2 igs1 igs0 gain (db) 00 00 00 16 01 012 01 118 10 020 10 126 11 032 11 138 adc both adcs consist of an analog sigma-delta modulator and a digital antialiasing decimation filter. the sigma-delta modulator noise-shapes the signal and produces 1-bit samples at a dmclk/8 rate. this bit-stream, representing the analog input signal, is input to the antialiasing decimation filter. the decimation filter reduces the sample rate and increases the resolution. analog sigma-delta modulator the AD73522's input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. sigma-delta converters employ a technique known as oversampling where the sampling rate is many times the highest frequency of interest. in the case of the AD73522, the initial sampling rate of the sigma-delta modulator is dmclk/ 8. the main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to f s /2 = dmclk/16 (figure 4a). this means that the noise in the band of interest is much reduced. another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. this technique has the effect of pushing the noise from the band of interest to an out- of-band position (figure 4b). the combination of these techniq ues, followed by the application of a digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (figure 4c). band of interest fs/2 dmclk/16 a. band of interest noise shaping fs/2 dmclk/16 b. band of interest fs/2 dmclk/16 digital filter c. figure 4. sigma-delta noise reduction figure 5 shows the various stages of filtering that are employed in a typical AD73522 application. in figure 5a we see the transfer function of the external analog antialias filter. even though it is a single rc pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (dmclk/8) that it takes care of any signals that could be aliased by the sampling frequency. this also shows the major difference between the initial oversampling rate and the bandwidth of interest. in figure 5b, the signal and noise shaping responses of the sigma-delta modulator are shown. the signal response provides further rejection of any high frequency signals while the noise shaping will push the inherent quantization noise to an out-of-band position. the detail of figure 5c shows the response of the digital decimation filter (sinc-cubed response) with nulls every multiple of dmclk/256, which corresponds to the decimation filter update rate for a 64khz sampling. the nulls of the sinc3 response correspond with multiples of the chosen sampling frequency. the final detail in figure 5d shows the application of a final antialias filter in the dsp engine. this has the advantage of being implemented according to the users requirements and available mips. the filtering in figures 5a through 5c is implemented in the AD73522.
AD73522 C13C rev. prc 05/99 preliminary technical data preliminary technical data f b = 4khz fs init = dmclk/8 a. analog antialias filter transfer function f b = 4khz fs init = dmclk/8 signal transfer function noise transfer function b. analog sigma-delta modulator transfer function f b = 4khz fs inter = dmclk/256 c. digital decimator transfer function f b = 4khz fs final = 8khz fs inter = dmclk/256 d. final filter lpf (hpf) transfer function figure 5. AD73522 adc frequency responses decimation filter the digital filter used in the AD73522s afe section carries out two important f unctions. firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bit-stream to a lower rate 16-bit word. the antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from dmclk/8 to dmclk/ 256, and increases the resolution from a single bit to 15 bits or greater (depending on chosen sampling rate). its z trans- form is given as: [(1Cz Cn )/(1Cz C1 )] 3 where n is set by the sampling rate (n= 32 @ 64khz sampling .... n = 256 @ 8 khz sampling) thus when the sampling rate is 64khz a minimal group delay of 25 s can be achieved. word growth in the decimator is determined by the sampling rate. at 64khz sampling, where the over sampling ratio between sigma-delta modulator and decimator output equals 32, we get 5 bits per stage of the three stage sinc3 filter. due to symmetry within the sigma delta modulator, the lsb will always be a zero, therefore the 16 bit adc output word will have 2 lsbs equal to zero, one due to the sigma-delta symmetry and the other being a padding zero to make up the 16 bit word. at lower sampling rates, decimator word growth will be greater than the 16 bit sample word therefore truncation occurs in transferring the decimator output as the adc word. for example at 8 khz sampling, word growth reaches 24 bits due to the osr of 256 between sigma delta modulator and decimator output. this yields 8 bits per stage of the 3 stage sinc3 filter. adc coding the adc coding scheme is in twos complement format (see figure 6). the output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a word length of up to 18- bits (depending on decimation rate chosen), which is the final output of the adc block. in data mode this value is truncated to 16-bits for output on the serial data output (sdo) pin. for input values equal to or greater than positive full scale, however, the output word is set at 0x7fff, which has the lsb set to 1 . in mixed control/data mode, the resolution is fixed at 15 bits, with the msb of the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. v inn v inp v ref + (v ref x 0.32875) v ref v ref - (v ref x 0.32875) 10...00 00...00 01...11 adc code differential v inn v inp v ref + (v ref x 0.6575) v ref v ref - (v ref x 0.6575) 10...00 00...00 01...11 adc code single ended analog input analog input figure 6. adc transfer function decoder channel the decoder channels consist of digital interpolators, digital sigma-delta modulators, single bit digital-to-analog converters (dac), analog smoothing filters and programmable gain amplifiers with differential outputs. dac coding the dac coding scheme is in twos complement format with 0x7fff being full-scale positive and 0x8000 being full-scale negative. interpolation filter the anti-imaging interpolation filter is a sinc-cubed digital filter which up-samples the 16-bit input words from the input sample rate to a rate of dmclk/8 while filtering to
AD73522 C14C rev. prc 05/99 preliminary technical data preliminary technical data attenuate images produced by the interpolation process. its z transform is given as: [(1Cz Cn )/(1Cz C1 )] 3 where n is determined by the sampling rate (n = 32 @ 64khz ... n = 256 @ 8khz). the dac receives 16-bit samples from the host dsp processor at the programmed sample rate of dmclk/n. if the host processor fails to write a new value to the serial port, the existing (previous) data is read again. the data stream is filtered by the anti-imaging interpolation filter, but there is an option to bypass the interpolator for the minimum group delay configuration by setting the ibyp bit (cre:5) of control register e. the interpolation filter has the same characteristics as the adcs antialiasing decimation filter. the output of the interpolation filter is fed to the dacs digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples at a rate of dmclk/8. the modulator noise-shapes the signal so that errors inherent to the process are minimized in the passband of the converter. the bit- stream output of the sigma-delta modulator is fed to the single bit dac where it is converted to an analog voltage. analog smoothing filter & pga the output of the single-bit dac is sampled at dmclk/8, therefore it is necessary to filter the output to reconstruct the low frequency signal. the decoders analog smoothing filter consists of a continuous-time filter preceded by a third-order switched-capacitor filter. the continuous-time filter forms part of the output programmable gain amplifier (pga). the pga can be used to adjust the output signal level from C15 db to +6 db in 3 db steps, as shown in table ii. the pga gain is set by bits ogs0, ogs1 and ogs2 (crd:4-6) in control register d. table ii. pga settings for the decoder channel og2 og1 og0 gain (db) 00 0+6 00 1+3 01 00 01 1C3 10 0C6 10 1C9 1 1 0 C12 1 1 1 C15 differential output amplifiers the decoder has a differential analog output pair (voutp and voutn). the output channel can be muted by setting the mute bit (crd:7) in control register d. the output signal is dc-biased to the codecs on-chip voltage reference. voltage reference the AD73522 reference, refcap, is a bandgap reference that provides a low noise, temperature-compensated reference to the dac and adc. a buffered version of the reference is also made available on the refout pin and can be used to bias other external analog circuitry. the reference has a nominal value of 1.2 v. the reference output (refout) can be enabled for biasing external circuitry by setting the ru bit (crc:6) of crc. vinn1 vinp1 vfbn1 vfbp1 v ref voutp1 voutn1 continuous time low-pass filter +6/-15db pga v ref ad73422 afe section analog loopback select single-ended enable invert inverting op- amps analog gain tap gain +/- 1 0/38 db pga refout refcap reference figure 7. analog input/output section analog and digital gain taps the AD73522 features analog and digital feedback paths between input and output. the amount of feedback is deter- mined by the gain setting which is programmed in the control registers. this feature can typically be used for balancing the effective impedance between input and output when used in subscriber line interface circuit (slic) interfacing. analog gain tap the analog gain tap is configured as a programmable differen- tial amplifier whose input is taken from the adc's input signal path. the output of the analog gain tap is summed with the output of the dac. the gain is programmable using control register f (crf:0-4) to achieve a gain of -1 to +1 in 32 steps with muting being achieved through a separate control setting (control register f bit _). the gain increment per step is 0.0625. the agt is enabled by powering-up the agt control bit in the power control register (crc:1). when this bit is set (=1) crf becomes an agt control register with crf:0-4 holding the agt coefficient, crf:5 becomes an agt enable and crf:7 becomes an agt mute control bit. control bit crf:5 connects/disconnects the agt output to the summer block at the output of the dac section while control bit crf:7 overides the gain tap setting with a mute, or zero gain, setting (which is omitted from the gain settings). table iii shows the gain versus digital setting for the agt. table iii. analog gain tap settings agtc4 agtc3 agtc2 agtc1 agtc0 gain 00000 +1.00 00001+0.9375 00010 +0.875 00011+0.8125 00100 +0.0.75 ----- - 01111+0.0625 10000 -0.0625 ----- - 11101 -0.875 11110 C0.9375 11111 C1.00
AD73522 C15C rev. prc 05/99 preliminary technical data preliminary technical data digital gain tap the digital gain tap features a programmable gain block whose input is taken from the bitstream from the adc's sigma-delta modulator. this single bit input (1 or 0) is used to add or subtract a programmable value, which is the digital gain tap setting, to the output of the dac section's interpolator. the programmable setting has 16 bit resolution and is programmed using the settings in control registers g and h. table iv. digital gain tap settings dgt15-0 (hex) gain 0x8000 -1.00 0x9000 -0.875 0xa000 -0.75 0xc000 -0.5 0xe000 -0.25 0x0000 -0.00 0x2000 +0.25 0x4000 +0.5 0x6000 +0.75 0x7fff +0.99999 afe serial port (sport2) the afe section communicates with the dsp section via its bidirectional synchronous serial port (sport2) which interfaces to either sport0 or sport1 of the dsp section. sport2 is used to transmit and receive digital data and control information. the dual afe is implemented using two separate afe blocks which are internally cascaded with serial port access to the input of afe channel 1 and the output of afe channel 2. this allows other single or dual codec devices to be cascaded together (up to a limit of 8 codec units). in both transmit and receive modes, data is transferred at the serial clock (sclk2) rate with the msb being transferred first. communications between the afe section and the dsp section must always be initiated by the afe section (afe is in master mode - dsp sport is in slave mode). this ensures that there is no collision between input data and output samples. sport2 overview sport2 is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow extra afe devices (ad733xx series), up to a maximum of 8 afe blocks, to be connected in cascade to a dsp sport (0 or 1). it has a very flexible architecture that can be configured by programming two of the internal control registers in each afe block. sport2 has three distinct modes of operation: control mode, data mode and mixed control/data mode. note: as each afe has its own control section, the register settings in each must be programmed. the registers which control serial transfer and sample rate operation (cra & crb) must be programmed with the same values, otherwise incorrect operation may occur. in control mode (cra:0 = 0), the devices internal configu- ration can be programmed by writing to the eight internal control registers. in this mode, control information can be written to or read from the codec. in data mode (cra:0 = 1), information that is sent to the device is used to update the decoder section (dac), while the encoder section (adc) data is read from the device. in this mode, only dac and adc data is written to or read from the device. mixed mode (cra:0 = 1 and cra:1 = 1) allows the user to choose whether the information being sent to the device contains either control information or dac data. this is achieved by using the msb of the 16-bit frame as a flag bit. mixed mode reduces the resolution to 15 bits with the msb being used to indicate whether the information in the 16-bit frame is control information or dac/adc data. sport2 features a single 16-bit serial register that is used for both input and output data transfers. as the input and output data must share the same register there are some precautions that must be observed. the primary precaution is that no information must be written to sport2 without reference to an output sample event, which is when the serial register will be overwritten with the latest adc sample word. once sport2 starts to output the latest adc word then it is safe for the dsp to write new control or data words to the codec. in certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial registersee section on interfacing devices. the serial clock rate (crb:2C3) defines how many 16-bit words can be written to a device before the next output sample event will happen. the sport2 block diagram, shown in figure 8, details the blocks associated with codecs 1 and 2 including the eight control registers (aCh), external mclk to internal dmclk divider and serial clock divider. the divider rates are controlled by the setting of control register b. the AD73522 features a master clock divider that allows users the flexibility of dividing externally available high frequency dsp or cpu clocks to generate a lower frequency master clock internally in the codec which may be more suitable for either serial transfer or sampling rate requirements. the master clock divider has five divider options (1 default condition, 2, 3, 4, 5) that are set by loading the master clock divider field in register b with the appropriate code. once the internal device master clock (dmclk) has been set using the master clock divider, the sample rate and serial clock settings are derived from dmclk. the sport can work at four different serial clock (sclk) rates: chosen from dmclk, dmclk/2, dmclk/4 or dmclk/8, where dmclk is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. when working at the lower sclk rate of dmclk/8, which is intended for interfacing with slower dsps, the sport will support a maximum of two codecs in cascade (a single AD73522 or two ad73311s) with the sample rate of dmclk/256. sport2 register maps there are two register banks for each afe channel in the AD73522: the control register bank and the data register bank. the control register bank consists of eight read/write registers, each 8 bits wide. table ix shows the control register map for the AD73522. the first two control registers, cra and crb, are reserved for controlling serial activity. they hold settings for parameters such as serial clock rate, internal
AD73522 C16C rev. prc 05/99 preliminary technical data preliminary technical data master clock rate, sample rate and device count. as both codecs are internally cascaded, registers cra and crb on each codec must be programmed with the same setting to ensure correct operation (this is shown in the programming examples). the other five registers; crc through crh are used to hold control settings for the adc, dac, reference, power control and gain tap sections of the device. it is not necessary that the contents of crc through crh on each codec are similar. control registers are written to on the negative edge of sclk. the data register bank consists of two 16-bit registers that are the dac and adc registers. master clock divider the AD73522s afe features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin mclk, by one of the ratios 1, 2, 3, 4 or 5 to produce an internal master clock signal (dmclk) that is used to calculate the sampling and serial clock rates. the master clock divider is programmable by setting crb:4-6. table v shows the division ratio corresponding to the various bit settings. the default divider ratio is divide by one. table v. dmclk (internal) rate divider settings mcd2 mcd1 mcd0 dmclk rate 0 0 0 mclk 0 0 1 mclk/2 0 1 0 mclk/3 0 1 1 mclk/4 1 0 0 mclk/5 1 0 1 mclk 1 1 0 mclk 1 1 1 mclk serial clock rate divider the AD73522s afe features a programmable serial clock divider that allows users to match the serial clock (sclk) rate of the data to that of the dsp engine or host processor. the maximum sclk rate available is dmclk and the other available rates are: dmclk/2, dmclk/4 and dmclk/8. the slowest rate (dmclk/8) is the default sclk rate. the serial clock divider is programmable by setting bits crb:2C3. table vi shows the serial clock rate corresponding to the various bit settings. table vi. sclk rate divider settings scdi scd0 sclk rate 0 0 dmclk/8 0 1 dmclk/4 1 0 dmclk/2 1 1 dmclk sample rate divider the AD73522 features a programmable sample rate divider that allows users flexibility in matching the codec's adc and dac sample rates to the needs of the dsp software. the maximum sample rate available is dmclk/256 which offers the lowest conversion group delay, while the other available rates are: dmclk/512, dmclk/1024 and dmclk/2048. the slowest rate (dmclk/2048) is the default sample rate. the sample rate divider is programmable by setting bits crb:0-1. table vii shows the sample rate corresponding to the various bit settings. serial port 1 (sport1) serial register sclk divider mclk divider control register 1b control register 1a control register 1c control register 1d control register 1e mclk (external) se reset sdifs sdi dmclk (internal) 3 8 8 8 8 8 2 sclk (sdofs1) (sdo1) serial register 1 serial port 2 (sport2) serial register sclk divider mclk divider control register 2b control register 2a control register 2c control register 2d control register 2e mclk (external) se reset (sdifs2) (sdi2) dmclk (internal) 3 8 8 8 8 8 2 sdofs sdo serial register control register 1g control register 1h control register 1f 8 16 control register 2g control register 2h control register 2f 8 16 figure 8. sport2 block diagram
AD73522 C17C rev. prc 05/99 preliminary technical data preliminary technical data table vii. sample rate divider settings srdi srd0 sclk rate 00 dmclk/2048 01 dmclk/1024 10 dmclk/512 11 dmclk/256 dac advance register the loading of the dac is internally synchronized with the unloading of the adc data in each sampling interval. the default dac load event happens one sclk cycle before the sdofs flag is raised by the adc data being ready. however, this dac load position can be advanced before this time by modifying the contents of the dac advance field in control register e (cre:0C4). the field is five-bits wide, allowing 31 table x. control word description control frame description bit 15 control/data when set high, it signifies a control word in program or mixed program/data modes. when set low, it signifies a data word in mixed program/data mode or an invalid control word in program mode. bit 14 read/write when set low, it tells the device that the data field is to be written to the register selected by the register field setting provided the address field is zero. when set high, it tells the device that the selected register is to be written to the data field in the input serial register and that the new control word is to be output from the device via the serial output. bit 13C11 device address this 3-bit field holds the address information. only when this field is zero is a device selected. if the address is not zero, it is decremented and the control word is passed out of the device via the serial output. bits 10C8 register address this 3-bit field is used to select one of the five control registers on the ad73322. bits 7C0 register data this 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero. table ix. control register map address (binary) name description type width reset setting (hex) 000 cra control register a r/w 8 0x00 001 crb control register b r/w 8 0x00 010 crc control register c r/w 8 0x00 011 crd control register d r/w 8 0x00 100 cre control register e r/w 8 0x00 100 crf control register f r/w 8 0x00 100 crg control register g r/w 8 0x00 100 crh control register h r/w 8 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c/ dr/ w device address register address register data increments of weight 1/(f s *32); see table viii. the sample rate f s is dependent on the setting of both the mclk divider and the sample rate divider; see tables vii and ix. in certain circumstances this dac update adjustment can reduce the group delay when the adc and dac are used to process data in series. appendix _ details how the dac advance feature can be used. note: the dac advance register should not be changed while the dac section is powered up. table viii. dac timing control da4 da3 da2 da1 da0 time advance 000 0 0 0 s 0 0 0 0 1 1/(f s *32) s 0 0 0 1 0 2/(f s *32) s 1 1 1 1 0 30/(f s *32) s 1 1 1 1 1 31/(f s *32) s
AD73522 C18C rev. prc 05/99 preliminary technical data preliminary technical data table xi. control register a description control register a bit name description 0 data/pgm operating mode (0 = program; 1 = data mode) 1 mm mixed mode (0 = off; 1 = enabled) 2 dlb digital loop-back mode (0 = off; 1 = enabled) 3 slb sport loop-back mode (0 = off; 1 = enabled) 4 dc0 device count (bit 0) 5 dc1 device count (bit 1) 6 dc2 device count (bit 2) 7 reset software reset (0 = off; 1 = initiates reset) table xii. control register b description control register b bit name description 0 dir0 decimation/interpolation rate (bit 0) 1 dir1 decimation/interpolation rate (bit 1) 2 scd0 serial clock divider (bit 0) 3 scd1 serial clock divider (bit 1) 4 mcd0 master clock divider (bit 0) 5 mcd1 master clock divider (bit 1) 6 mcd2 master clock divider (bit 2) 7 cee control echo enable (0 = off; 1 = enabled) table xiii. control register c description control register c bit name description 0 pu power-up device (0 = power down; 1 = power on) 1 puagt analog gain tap power (0 = power down; 1 = power on) 2 puia input amplifier power (0 = power down; 1 = power on) 3 puadc adc power (0 = power down; 1 = power on) 4 pudac dac power (0 = power down; 1 = power on) 5 puref ref power (0 = power down; 1 = power on) 6 ru refout use (0 = disable refout; 1 = enable refout) 7 - reserved (must be programmed to 0) 76 543 210 reset dc2 dc1 dc0 slb dlb mm data/ pgm 76 5 43 2 1 0 cee mcd2 mcd1 mcd0 scd1 scd0 dir1 dir0 76 5 43 21 0 - ru puref pudac puadc puia puagt pu
AD73522 C19C rev. prc 05/99 preliminary technical data preliminary technical data table xvi. control register d description control register d bit name description 0 igs0 input gain select (bit 0) 1 igs1 input gain select (bit 1) 2 igs2 input gain select (bit 2) 3 rmod reset adc modulator (0 = off; 1 = reset enabled) 4 ogs0 output gain select (bit 0) 5 ogs1 output gain select (bit 1) 6 ogs2 output gain select (bit 2) 7 mute output mute (0 = mute off; 1 = mute enabled) table xiv. control register e description control register e bit name description 0 da0 dac advance setting (bit 0) 1 da1 dac advance setting (bit 1) 2 da2 dac advance setting (bit 2) 3 da3 dac advance setting (bit 3) 4 da4 dac advance setting (bit 4) 5 ibyp interpolator bypass (0 = bypass disabled; 1 = bypass enabled) 6 dgte digital gain tap enable (0 = disabled; 1 = enabled) 7 tme test mode enable (0 = disabled; 1 = enabled) table xv. control register f description control register f bit name description 0 agtc0 analog gain tap coefficient (bit 0) 1 agtc1 analog gain tap coefficient (bit 1) 2 agtc2 analog gain tap coefficient (bit 2) 3 agtc3 analog gain tap coefficient (bit 3) 4 agtc4 analog gain tap coefficient (bit 4) 5 seen single-ended enable (0 = disabled; 1 = enabled) agte analog gain tap enable (0 = disabled; 1 = enabled) 6 inv input invert(0 = disabled; 1 = enabled) 7 alb analog loopback of output to input (0 = disabled; 1 = enabled) agtm analog gain tap mute (0 = off; 1 = muted) 76 543 210 mute ogs2 ogs1 ogs0 rmod igs2 igs1 igs0 76 5 43 21 0 tme dgte ibyp da4 da3 da2 da1 da0 76 543 210 alb/ inv seen/ agtc4 agtc3 agtc2 agtc1 agtc0 agtm agte
AD73522 C20C rev. prc 05/99 preliminary technical data preliminary technical data table xvi. control register g description control register g bit name description 0 dgtc0 d igital gain tap coefficient (bit 0) 1 dgtc1 d igital gain tap coefficient (bit 1) 2 dgtc2 d igital gain tap coefficient (bit 2) 3 dgtc3 d igital gain tap coefficient (bit 3) 4 dgtc4 d igital gain tap coefficient (bit 4) 5 dgtc5 d igital gain tap coefficient (bit 5) 6 dgtc6 d igital gain tap coefficient (bit 6) 7 dgtc7 d igital gain tap coefficient (bit 7) table xvii. control register h description control register h bit name description 0 dgtc8 d igital gain tap coefficient (bit 8) 1 dgtc9 d igital gain tap coefficient (bit 9) 2 dgtc10 digital gain tap coefficient (bit 10) 3 dgtc11 digital gain tap coefficient (bit 11) 4 dgtc12 digital gain tap coefficient (bit 12) 5 dgtc13 digital gain tap coefficient (bit 13) 6 dgtc14 digital gain tap coefficient (bit 14) 7 dgtc15 digital gain tap coefficient (bit 15) 76 5 43 21 0 dgtc7 dgtc6 dgtc5 dgtc4 dgtc3 dgtc2 dgtc1 dgtc0 76 5 43 21 0 dgtc15dgtc14 dgtc13 dgtc12dgtc11 dgtc10 dgtc9 dgtc8
AD73522 C21C rev. prc 05/99 preliminary technical data preliminary technical data operation resetting the AD73522s afe the pin resetc resets all the control registers. all registers are reset to zero indicating that the default sclk rate (dmclk/8) and sample rate (dmclk/2048) are at a minimum to ensure that slow speed dsp engines can communicate effectively. as well as resetting the control registers using the resetc pin, the device can be reset using the reset bit (cra:7) in control register a. both hardware and software resets require 4 dmclk cycles. on reset, data/ pgm (cra:0) is set to 0 (default condition) thus enabling program mode. the reset conditions ensure that the device must be programmed to the correct settings after power-up or reset. following a reset, the sdofs will be asserted 280 dmclk cycles after resetc going high. the data that is output following reset and during program mode is random and contains no valid information until either data or mixed mode is set. power management the individual functional blocks of the AD73522 can be enabled separately by programming the power control register crc. it allows certain sections to be powered down if not required, which adds to the devices flexibility in that the user need not incur the penalty of having to provide power for a certain section if it is not necessary to their design. the power control registers provides individual control settings for the major functional blocks on each codec unit and also a global override that allows all sections to be powered up by setting the bit. using this method the user could, for example, individually enable a certain section, such as the reference (crc:5), and disable all others. the global power-up (crc:0) can be used to enable all sections but if power-down is required using the global control, the reference will still be enabled, in this case, because its individual bit is set. refer to table xiii for details of the settings of crc. note: as both codec units share a common reference, the reference control bits (crc:5-7) in each sport are wire ored to allow either device to control the reference. hence the reference is only in a reset state when the relevent control bit of both codec units is set to 0. afe operating modes there are three main modes of operation available on the AD73522; program, data and mixed program/data modes. there are also two other operating modes which are typically reserved as diagnostic modes; digital and sport loopback. the device configurationregister settings can be chan ged only in program and mixed program/data modes. in all modes, transfers of information to or from the device occur in 16-bit packets, therefore the dsp engines sport will be programmed for 16-bit transfers. program (control) mode in program mode, cra:0 = 0, the user writes to the control registers to set up the device for desired operationsport operation, cascade length, power management, input/output gain, etc. in this mode, the 16-bit information packet sent to the device by the dsp engine is interpreted as a control word whose format is shown in table x. in this mode, the user must address the device to be programmed using the address field of the control word. this field is read by the device and if it is zero ( 000 bin) then the device recognizes the word as being addressed to it. if the address field is not zero, it is then decremented and the control word is passed out of the deviceeither to the next device in a cascade or back to the dsp engine. this 3-bit address format allows the user to uniquely address any one of up to eight devices in a cascade; please note that this addressing scheme is valid only in sending control information to the device a different format is used to send dac data to the device(s). as the AD73522 features a dual afe, these two channels have separate device addresses for programming purposes - the two device addresses correspond to 0 and 1. following reset, when the se pin is enabled, the codec re- sponds by raising the sdofs pin to indicate that an output sample event has occurred. control words can be written to the device to coincide with the data being sent out of the sport or they can lag the output words by a time interval that should not exceed the sample interval. after reset, output frame sync pulses will occur at a slower default sample rate, which is dmclk/2048, until control register b is program- med after which the sdofs pulses will revert to the dmclk/ 256 rate. during program mode, the data output by the adcs is random and should not be interpreted as valid data. data mode once the device has been configured by programming the correct settings to the various control registers, the device may exit program mode and enter data mode. this is done by programming the data/pgm (cra:0) bit to a 1 and mm (cra:1) to 0. once the device is in data mode, the 16- bit input data frame is now interpreted as dac data rather than a control frame. this data is therefore loaded directly to the dac register. in data mode, as the entire input data frame contains dac data, the device relies on counting the number of input frame syncs received at the sdifs pin. when that number equals the device count stored in the device count field of cra, the device knows that the present data frame being received is its own dac update data. when the device is in normal data mode (i.e., mixed mode disabled), it must receive a hardware reset to reprogram any of the control register settings. in a single AD73522 configu- ration, each 16-bit data frame sent from the dsp to the device is i nterpreted as dac data but it is necessary to send two dac words per sample period in order to ensure dac update. also as the device count setting defaults to 1, it must be set to 2 (001b) to ensure correct update of both dacs on the AD73522. mixed program/data mode this mode allows the user to send control words to the device along with the dac data. this permits adaptive control of the device whereby control of the input/output gains can be effected by interleaving control words along with the normal flow of dac data. the standard data frame remains 16 bits, but now the msb is used as a flag bit to indicate whether the remaining 15 bits of the frame represent dac data or control information. in the case of dac data, the 15 bits are loaded with msb justification and lsb set to 0 to the dac register. mixed mode is enabled by setting the mm bit (cra:1) to 1 and the data/pgm bit (cra:0) to 1. in the case where control setting changes will be required during normal opera- tion, this mode allows the ability to load both control and data information with the slight inconvenience of formatting
AD73522 C22C rev. prc 05/99 preliminary technical data preliminary technical data the data. note that the output samples from the adc will also have the msb set to zero to indicate it is a data word. a description of a single device operating in mixed mode is detailed in appendix b, while appendix d details the initial- ization and operation of a dual codec cascade operating in mixed mode. note that it is not essential to load the control registers in program mode before setting mixed mode active. it is also possible to initiate mixed mode by programming cra with the first control word and then interleaving control words with dac data. digital loop-back this mode can be used for diagnostic purposes and allows the user to feed the adc samples from the adc register directly to the dac register. this forms a loop-back of the analog input to the analog output by reconstructing the encoded signal using the decoder channel. the serial interface will continue to work, which allows the user to control gain settings, etc. only when dlb is enabled with mixed mode operation can the user disable the dlb, otherwise the device must be reset. sport loop-back this mode allows the user to verify the dsp interfacing and connection by writing words to the sport of the devices and have them returned back unchanged after a delay of 16 sclk cycles. the frame sync and data word that are sent to the device are returned via the output port. again, slb mode can only be disabled when used in conjunction with mixed mode, otherwise the device must be reset. analog loop-back in analog loop-back mode, the differential dac output is connected, via a loopback switch, to the adc input. this mode allows the adc channel to check functionality of the dac channel as the reconstructed output signal can be monitored using the adc as a sampler. analog loop-back is enabled by setting the alb bit (crf:7) note: analog loop-back can only be enabled if the analog gain tap is powered-down (crc:1 = 0). gain +/- 1 vinn1 vinp1 vfbn1 vfbp1 v ref voutp1 voutn1 continuous time low-pass filter +6/-15db pga v ref ad73422 afe section analog loopback enabled single-ended enable invert inverting op- amps analog gain tap powered down 0/38 db pga refout refcap reference figure 9. analog loop-back connectivity afe interfacing the afe section sport (sport2) can be interfaced to either sport0 or sport1 of the dsp section. both serial input and output data use an accompanying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. the serial clock (sclk) is an output from the codec and is used to define the serial transfer rate to the dsps tx and rx ports. two primary configurations can be used: the first is shown in figure 10 where the dsps tx data, tx frame sync, rx data and rx frame sync are connected to the codecs sdi, sdifs, sdo and sdofs respectively. this co nfiguration, referred to as indirectly coupled or non frame sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. the delay between receipt of codec output data and transmission of input data for the codec is determined by the dsps software latency. when programming the dsp serial port for this con- figuration, it is necessary to set the rx fs as an input and the tx fs as an output generated by the dsp. this configuration is most useful when operating in mixed mode, as the dsp has the ability to decide how many words (either dac or control) can be sent to the codecs. this means that full control can be implemented over the device configuration as well as updating the dac in a given sample interval. the second configura- tion (shown in figure 11) has the dsps tx data and rx data connected to the codecs sdi and sdo, respectively while the dsps tx and rx frame syncs are connected to the codecs sdifs and sdofs. in this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the codec is forced to be synchronous with the output data from the codec. the dsp must be programmed so that both the tx fs and rx fs are inputs as the codec sdofs will be input to both. this configuration guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal data mode. note that when programming the dsp in this configuration it is advisable to preload the tx register with the first control word to be sent before the codec is taken out of reset. this ensures that this word will be transmitted to coincide with the first output word from the device(s). afe section sdifs sdi sclk2 sdo sdofs tfs(0/1) dt(0/1) sclk(0/1) dr(0/1) rfs(0/1) dsp section channel 1 channel 2 ad73422 figure 10. indirectly coupled or non frame sync loop- back configuration cascade operation the AD73522 has been designed to support cascading of extra external afes from either sport0 or sport1. cascaded operation can support mixes of dual or single channel devices with maximum number of codec units being eight (the AD73522 has two codec units configured on the device). the sport2 interface protocol has been designed so that device addressing is built into the packet of information sent to the device. this allows the cascade to be
AD73522 C23C rev. prc 05/99 preliminary technical data preliminary technical data formed with no extra hardware overhead for control signals or addressing. a cascade can be formed in either of the two modes previously discussed. there may be some restrictions in cascade operation due to the number of devices configured in the cascade and the sampling rate and serial clock rate chosen. the following relationship details the restrictions in configuring a codec cascade. number of codecs * word size(16) * sampling rate <= serial clock rate afe section sdifs sdi sclk2 sdo sdofs tfs(0/1) dt(0/1) sclk(0/1) dr(0/1) rfs(0/1) dsp section channel 1 channel 2 ad73422 figure 11. directly coupled or frame sync loop- back configuration when using the indirectly coupled frame sync configuration in cascaded operation it is necessary to be aware of the restrictions in sending data to all devices in the cascade. effectively the time allowed is given by the sampling interval (m/dmclk - where m can be one of 256, 512, 1024 or 2048) which is 125 s for a sample rate of 8 khz. in this interval, the dsp must transfer n 16 bits of information where n is the number of devices in the cascade. each bit will take 1/sclk and, allowing for any latency between the receipt of the rx interrupt and the transmission of the tx data, the relationship for successful operation is given by: m /dmclk > (( n/sclk ) + t interrupt latency ) the interrupt latency will include the time between the adc sampling event and the rx interrupt being generated in the dspthis should be 16 sclk cycles. as the AD73522 is configured in cascade mode, each device must know the number of devices in the cascade because the data and mixed modes use a method of counting input frame sync pulses to decide when they should update the dac register from the serial input register. control register a contains a 3-bit field (dc0C2) that is pro- grammed by the dsp during the programming phase. the default condition is that the field contains 000b, which is equivalent to a single device in cascade (see table xviii). however, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade, which is 001b for a single AD73522 device configuration. table xviii. device count settings dc2 dc1 dc0 cascade length 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8
AD73522 C24C rev. prc 05/99 preliminary technical data preliminary technical data functional description - dsp the AD73522 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single processor cycle. the AD73522 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 16k pm (optional 8k) timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode 16k dm (optional 8k) serial port ref adc1 adc2 dac1 dac2 analog front end section sport 2 figure 12. functional block diagram figure 12 is an overall block diagram of the AD73522. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. the s hifter can be used to efficiently implement numeric format control including multiword and block floating- point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the AD73522 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off- chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. program memory can store both instructions and data, per- mitting the AD73522 to fetch two operands in a single cycle, one from program memory and one from data memory. the AD73522 can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory con- nection, the AD73522 may be configured for 16-bit internal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct access to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with program- mable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh , and bg ). one execution mode (go mode) allows the AD73522 to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the AD73522 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the AD73522 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit
AD73522 C25C rev. prc 05/99 preliminary technical data preliminary technical data register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the AD73522 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the AD73522 sports. for additional information on serial ports, refer to the adsp-2100 family users manual , third edition. ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and -law companding accord- ing to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24- or 32-word, time-division multiplexed, serial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. dsp section pin descriptions the AD73522 will be available in a 119 ball pbga package. in order to maintain maximum functionality and reduce pack- age size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed func- tionality. the external bus pins are configured during re- set only, while serial port pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. in cases where pin functionality is reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics. see pin descriptions on page 10. memory interface pins the AD73522 processor can be used in one of two modes, full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. see tables for full memory mode pins and host mode pins for descriptions. full memory mode pins (mode c = 0) pin # of input/ name(s) pins output function a13:0 14 o address output pins for program, data, byte and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) pin # of input/ name(s) pins output function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, pro- gram, data or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge configur- able in mode d; open source in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dms and ioms signals terminating unused pin the following table shows the recommendations for terminating unused pins. pin terminations i/o hi-z* pin 3-state reset caused unused name (z) state by configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br, ebr float iad12:0 i/o (z) hi-z is float a0 o (z) hi-z br, ebr float d23:8 i/o (z) hi-z br, ebr float d7 or i/o (z) hi-z br, ebr float iwr i i high (inactive) d6 or i/o (z) hi-z br, ebr float ird i i br, ebr high (inactive) d5 or i/o (z) hi-z float ial i i low (inactive) d4 or i/o (z) hi-z br, ebr float is i i high (inactive) d3 or i/o (z) hi-z br, ebr float iack float d2:0 or i/o (z) hi-z br, ebr float iad15:13 i/o (z) hi-z is float pms o (z) o br, ebr float dms o (z) o br, ebr float bms o (z) o br, ebr float ioms o (z) o br, ebr float cms o (z) o br, ebr float rd o (z) o br, ebr float
AD73522 C26C rev. prc 05/99 preliminary technical data preliminary technical data pin terminations (continued) i/o hi-z* pin 3-state reset caused unused name (z) state by configuration wr o (z) o br, ebr float br i i high (inactive) bg o (z) o ee float bgh o o float irq2/pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql1/pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql0/pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float irqe/pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o o high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/rq0 i/o i high or low dr1/fi i i high or low tfs1/rq1 i/o o high or low dt1/fo o o float ee i i ebr i i ebg o o ereset i i ems o o eint i i eclk i i elin i i elout o o notes * *hi-z = high impedance. 1. if the clkout pin is not used, turn it off. 2. if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1, and let them float. 3. all bidirectional pins have three-stated outputs. when the pins is configured as an output, the output is hi-z (high impedance) when inactive. 4. clkin, reset, and pf3:0 are not included in the table because these pins must be used. interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the AD73522 provides four dedicated external interrupt input pins, irq2 , irql0 , irql1 and irqe . in addition, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the AD73522 also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power- down control circuit. the interrupt levels are internally prioritized and individually maskable (except power down and reset). the irq2 , irq0 and irq1 input pins can be pro- grammed to be either level- or edge-sensitive. irql0 and irql1 are level- sensitive and irqe is edge sensitive. the priorities and vector addresses of all interrupts are shown in table xix. table xix. interrupt priority and interrupt vector ad- dresses interrupt vector source of interrupt address (hex) reset (or power-up with pucr = 1) 0000 ( highest priority ) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 ( lowest priority ) interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. inter- rupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked int errupt is then selected. the power-down interrupt is nonmaskable. the AD73522 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port auto- buffering or dma transfers. the interrupt control register, icntl, controls interrupt nesting and defines the irq0 , irq1 and irq2 external inter- rupts to be either edge- or level-sensitive. the irqe pin is an external edge-sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are external level-sensi- tive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automatic ally maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt, loop and subroutine nesting. the following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the AD73522 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? power-down ? idle ? slow idle
AD73522 C27C rev. prc 05/99 preliminary technical data preliminary technical data the clkout pin may also be disabled to reduce external power dissipation. power-down the AD73522 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. here is a brief list of power-down features. refer to the adsp-2100 family users manual , third edition, system interface chapter, for detailed information about the power-d own feature. ? quick recovery from power-down. the processor begins executing instructions in as few as 400 clkin cycles. ? support for an externally generated ttl or cmos proces- sor clock. the external clock can continue running during power-down without affecting the 400 clkin cycle recov- ery. ? support for crystal operation includes disabling the oscilla- tor to save power (the processor automatically waits 4096 clkin cycles for the crystal oscillator to start and stabi- lize), and letting the oscillator run to allow 400 clkin cycle start up. ? power-down is initiated by either the power-down pin ( pwd ) or the software power-down force bit interrupt support allows an unlimited number of instructions to be executed before optionally powering down. the power- down interrupt also can be used as a non-maskable, edge- sensitive interrupt. ? context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power- down. ? power-down acknowledge pin indicates when the processor has entered power-down. idle when the AD73522 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occ urs. when an unmasked interrupt occurs, it is serviced; exe cution then continues with the instruction following the idle instruction. in i dle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction on the AD73522 slows the processors internal clock signal, further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64 or 128. this instruction keeps the pro- cessor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout and timer clock, are re- duced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruc- tion. when the idle (n) instruction is used, it effectively slows down the processors internal clock and thus its response time to incoming interrupts. the one-cycle response time of the standard idle state is increased by n , the clock divisor. when an enabled interrupt is received, the AD73522 will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64 or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 13 shows a typical basic system configuration with the AD73522, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode selectable). programmable wait state generation allows the processor to connect easily to slow peripheral devices. the AD73522 also provides four external interrupts and two serial ports or six external interrupts and one serial port. host memory mode allows access to the full external data bus, but limits addressing to a single address bit (a0) additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. clock signals the AD73522 can be clocked by either a crystal or a ttl- compatible clock signal. the clkin input cannot be halted, changed during operation or operated below the specified frequency during normal operation. the only exception is while the processor is in the power-d own state. for additional information, refer to chapter 9, adsp-2100 family users manual, third edition, for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is con- nected to the processors clkin input. when an external clock is used, the xtal input must be left unconnected.
AD73522 C28C rev. prc 05/99 preliminary technical data preliminary technical data 1/2x clock or crystal afe* sectiono r serial device sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 a0-a21 data cs byte memory i/o space (peripherals) cs data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments d 23-0 a 13-0 d 23-8 a 10-0 d 15-8 d 23-16 a 13-0 14 24 fl0-2 pf3 clkin xtal addr13-0 data23-0 bms ioms pms dms cms br bg bgh pwd pwdack ad73422 1/2x clock or crystal afe* section or serial device system interface or m controller 16 1 16 sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 iad15-0 idma port fl0-2 pf3 clkin xtal a0 data23-8 bms ioms pms dms cms br bg bgh pwd pwdack ad73422 irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf0 mode a/pf1 host memory mode irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf0 mode a/pf1 full memory mode ird /d6 iwr /d7 is /d4 sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi afe* section or serial device ial/d5 iack /d3 wr rd wr rd afe* section or serial device *afe section can be connected to either sport0 or sport1 figure 13. AD73522 basic system configuration the AD73522 uses an input clock with a frequency equal to half the instruction rate; a 26.00 mhz input clock yields a 19 ns processor cycle (which is equivalent to 52 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the AD73522 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors con- nected as shown in figure 14. capacitor values are dependent on crystal type and should be specified by the crystal manu- facturer. a parallel-resonant, fundamental frequency, microprocessor- grade crystal should be used. a clock output (clkout) signal is generated by the proces- sor at the processors cycle rate. this can be enabled and disabled by the clk0dis bit in the sport0 autobuffer control register. clkin clkout xtal dsp figure 14. external crystal connections reset the reset signal initiates a master reset of the AD73522. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power- up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is applied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked, but does not include the crystal oscillator start-up time. during this power-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . the reset input contains some hysteresis; however, if an rc circuit is used to generate the reset signal, an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot- loading sequence is performed. the first instruction is fetched from on-chip program memory loca tion 0x0000 once boot loading completes. modes of operation table xx summarizes the AD73522 memory modes. setting memory mode memory mode selection for the AD73522 is made during chip reset through the use of the mode c pin. this pin is multiplexed with the dsps pf2 pin, so care must be taken in how the mode selection is made. the two methods for selecting the value of mode c are active and passive. passive configuration involves the use a pull-up or pull- down resistor connected to the mode c pin. to minimize power consu mption, or if the pf2 pin is to be used as an output in the dsp application, a weak pull-up or pull-down, on the order of 100 k y , can be used. this value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processors output driver. for minimum power consumption during power-down, reconfigure pf2 to be an input, as the
AD73522 C29C rev. prc 05/99 preliminary technical data preliminary technical data pull-up or pull-down will hold the pin in a known state, and will not switch. active configuration involves the use of a three-statable external driver connected to the mode c pin. a drivers output enable should be connected to the dsps reset signal such that it only drives the pf2 pin when reset is active (low). when reset is deasserted, the driver should three-state, thus allowing full use of the pf2 pin as either an input or output. to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three-stated buffer. this ensures that the pin will be held at a constant level and not oscillate should the three-state drivers level hover around the logic switching point. memory architecture the AD73522 provides a variety of memory and peripheral interface options. the key functional groups are program memory, data memory, byte memory, and i/o. refer to the following figures and tables for pm and dm memory alloca- tions in the AD73522. program memory program memory (full memory mode) is a 24-bit-wide space for storing both instruction opcodes and data. the AD73522-80 has 16k words of program memory ram on chip (the AD73522-40 has 8k words of program memory ram on chip), and the capability of accessing up to two 8k external memory overlay spaces using the external data bus . program memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a restricted data bus that is 16-bits wide only. table xxi. pmovlay bits pmovlay memory a13 a12:0 0, internal not applicable not applicable 1 external 0 13 lsbs of ad- dress overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of ad- dress overlay 2 between 0x2000 and 0x3fff accessible when pmovlay = 2 accessible when pmovlay = 1 always accessible at address 0 x 0000 - 0 x 1fff accessible when pmovlay = 0 3 pm (mode b = 0) internal memory external memory 0 x2000- 0x3fff 0 x2000- 0x3fff 2 0 x2000- 0x3fff 2 8k internal pmovlay = 0 3 8k external program memory mode b = 1 address 0 x 3fff 0 x 2000 0 x 1fff 0 x 0000 8k internal pmovlay = 0 3 or 8k external pmovlay = 1 or 2 0 x 3fff 0 x 2000 0 x 1fff 8k internal 0 x 0000 program memory mode b = 0 address accessible when pmovlay = 0 internal memory external memory 0 x2000- 0x3fff 0 x0000- 0x1fff 2 pm (mode b = 1) 1 reserved 1 when mode b = 1, pmovlay must be set to 0 2 see table iii for pmovlay bits 3 not accessible on ad73422-40 accessible when pmovlay = 0 3 reserved figure 15. program memory map table xxi. modes of operations 1 mode c 2 mode b 3 mode a 4 booting method 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. 5 0 1 0 no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used, but the processor does not automatically use or wait for these operations. 1 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode. (requires additional hardware.) 1 0 1 idma feature is used to load any internal memory as desired. program execution is held off until internal program memory location 0 is written to. chip is configured in host mode. 5 notes 1 all mode pins are recognized while reset is active (low). 2 when mode c = 0, full memory enabled. when mode c = 1, host memory mode enabled. 3 when mode b = 0, auto booting enabled. when mode b = 1, no auto booting. 4 when mode a = 0, bdma enabled. when mode a = 1, idma enabled. 5 considered as standard operating settings. using these configurations allows for easier design and better memory management.
AD73522 C30C rev. prc 05/99 preliminary technical data preliminary technical data data memory data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the AD73522-80 has 16k words on data memory ram on chip (the AD73522-40 has 8k words on data memory ram on chip), consisting of 16,352 user- accessible locations in the case of the AD73522-80 ( 8,160 user-accessible locations in the case of the AD73522-40) and 32 memory-mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. accessible when dmovlay = 2 accessible when dmovlay = 1 32 memory mapped registers 0 x 3fff 0 x 2000 0 x 1fff internal 8160 words 0 x 0000 data memory address always accessible at address 0 x 2 000 - 0 x 3 fff accessible when dmovlay = 0 1 internal memory external memory 0 x 0000- 0 x 1 1fff 0 x 0000- 0 x 1fff 0 x 0000- 0 x 1fff data memory 8k internal dmovlay = 0 1 or external 8k dmovlay = 1, 2 0 x 3fe0 0 x 3fdf 1 not accessible on ad73422-40 figure 16. data memory map data memory (host mode) allows ac cess to all inte rnal memory. external overlay access is limited by a single external address line (a0). the dmovlay bits are defined in table xxii. table xxii. dmovlay bits dmovlay memory a13 a12:0 0, internal not applicable not applicable 1 external 0 13 lsbs of ad- dress overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of ad- dress overlay 2 between 0x2000 and 0x3fff i/o space (full memory mode) the AD73522 supports an additional external memory space called i/o space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data registers. i/o space supports 2048 locations of 16-bit wide data. the lower eleven bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedi- cated 3-bit wait state registers, iowait0-3, that specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges as shown in table xxiii. table xxiii. wait states address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 composite memory select ( cms cms cms cms cms ) the AD73522 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is gener- ated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can combine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is as- serted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory; use either dms or pms as the additional address bit. the cms pin functions like the other memory select signals, with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits default to 1 at reset, except the bms bit. boot memory select ( bms bms bms bms bms ) disable the AD73522 also lets you boot the processor from one external memory space while using a different external memory space for bdma transfers during normal operation. you can use the cms to select the first external memory space for bdma transfers and bms to select the second external memory space for booting. the bms signal can be disabled by setting bit 3 of the system control register to 1. the system control register is illustrated in figure 17. 00000100 00000111 15 14 13 12 11 10 98 76543210 dm (0 3 3fff) system control register sport0 enable 1 = enabled, 0 = disabled sport1 enable 1 = enabled, 0 = disabled sport1 configure 1 = serial port 0 = f1, fo, irq0 , irq1 , sclk pwait program memory wait states bms enable 0 = enabled, 1 = disabled figure 17. system control register byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the bdma control register is shown in figure 18. the byte memory space con- sists of 256 pages, each of which is 16k 8. the byte memory space on the AD73522 supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or
AD73522 C31C rev. prc 05/99 preliminary technical data preliminary technical data ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally, and steals only one dsp cycle per 8-, 16- or 24-bit word transferred. bdma control bmpage bdma overlay bits btype bdir 0 = load from bm 1 = store to bm bcr 0 = run during bdma 1 = halt during bdma 0 000 0000 000 010 00 1 5 1 4 1 3 1 2 1 1 1 0 98 7654 3210 dm (0 3 3fe3) figure 18. bdma control register the bdma circuit supports four different data formats that are selected by the btype register field. the appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. table xxiv shows the data formats supported by the bdma circuit. table xxiv. data formats internal btype memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the starting page for the external byte memory space. the bdir register field selects the direction of the transfer. finally the 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is generated. the bmpage and bead registers must not be accessed by the dsp during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one dsp cycle. dsp accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether or not the processor is held off while the bdma accesses are occur- ring. setting the bcr bit to 0 allows the processor to continue operations. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor and start execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communication between a host system and the AD73522. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot be used, however, to write to the dsps memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer. 2. host checks iack control line to see if the dsp is busy. 3. host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the dsps idma control registers. if iad[15] = 1, the value of iad[7:0] represent the idma overlay: iad[14:8] must be set to 0. if iad[15] = 0, the value of iad[13:0] represent the starting address of internal memory to be accessed and iad[14] reflects pm or dm for access. 4. host uses is and ird (or iwr ) to read (or write) dsp internal memory (pm or dm). 5. host checks iack line to see if the dsp has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is completely asynchronous and can be written to while the AD73522 is operating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this in- creases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma add ress latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on- chip memory location; the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register.
AD73522 C32C rev. prc 05/99 preliminary technical data preliminary technical data once the address is stored, data can either be read from or written to the AD73522s on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the AD73522 that a particular transaction is required. in either case, there is a one- processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented and another access can occur. through the idmaa register, the dsp can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the AD73522 to write the address onto the iad0C14 bus into the idma control register. if iad[15] is set to 0, idma latches the address. if iad[15] is set to 1, idma latches ovlay memory. the idma ovlay and address are stored in s eparate memory-mapped registers. the idmaa register, shown below, is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) cannot be read back by the host. the idma ovlay register is memory mapped at address dm (0x3fe7). see figure 19 for more information on idma and dma memory maps. idma control (u = undefined at reset) dm(0 3 3fe0) idmaa address idmad destination memory type: 0 = pm 1 = dm u uuu uuuu uu uuuu u 1 5 1 4 1 3 1 2 1 1 1 0 98 765 4321 0 figure 19. idma control/ovlay registers bootstrap loading (booting) the AD73522 has two mechanisms to allow automatic load- ing of the internal program memory after reset. the method for booting after reset is controlled by the mode a, b and c configuration bits. when the mode pins specify bdma booting, the AD73522 initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma booting is specified: the bdir, bmpage, biad and bead registers are set to 0, the btype register is set to 0 to specify program memory 24- bit words, and the bwcount register is set to 32. this causes 32 words of on-chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the adsp-2100 family development software (revision 5.02 and later) fully supports the bdma booting feature and can generate byte memory space compatible boot code. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the addresses to boot memory must be constructed externally to the AD73522. the only memory address bit provided by the processor is a0. idma port booting the AD73522 can also boot programs through its internal dma port. if mode c = 1, mode b = 0 and mode a = 1, the AD73522 boots from the idma port. idma feature can load as much on-chip memory as desired. program execution is held off until on-chip program memory location 0 is written to. bus request and bus grant (full memory mode) the AD73522 can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request (br) signal. if the AD73522 is not performing an external memory access, it responds to the active br input in the following processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal, and ? halting program execution. if go mode is enabled, the AD73522 will not halt program execution until it encounters an instruction that requires an external memory access. if the AD73522 is performing an external memory access when the external device asserts the br signal, it will not three-state the memory interfaces or assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the AD73522 is ready to ex- ecute an instruction, but is stopped because the external bus is already granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the AD73522 deasserts bg and bgh and executes the external memory access. flag i/o pins the AD73522 has eight general purpose programmable input/output flag pins. they are controlled by two memory mapped registers. the pftype register determines the direc- tion, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the AD73522s clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the AD73522 has five fixed-mode flags, flag_in, flag_out, fl0, fl1 and fl2. fl0-fl2 are dedicated output flags. flag_in
AD73522 C33C rev. prc 05/99 preliminary technical data preliminary technical data and flag_out are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2 and pf3 are also used for device configuration during reset. instruction set description the AD73522 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full advantage of the processors unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize on-chip memory and conform to the AD73522s interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the AD73522 has on-chip emulation support and an ice- port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ices in-circuit probe, a 14-pin plug. see the adsp-2100 family ez-tools data sheet for complete information on ice products. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user interface. if you are using a passive method of maintaining mode information (as discussed in setting memory modes) then it does not matter that the mode information is latched by an emulator reset. however, if you are using the reset pin as a method of setting the value of the mode pins, then you have to take into consideration the effects of an emulator reset. one method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in figure 20. this circuit forces the value located on the mode a pin to logic high; regardless if it latched via the reset or ereset pin. ereset reset ad73422 mode a/pfo programmable i/o 1k v figure 20. mode a pin/ez-ice circuit the ice-port interface consists of the following AD73522 pins: ebr ebg ereset ems eint eclk elin elout ee these AD73522 pins must be connected only to the ez-ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull- down resistors. the traces for these signals between the AD73522 and the connector must be kept as short as pos- sible, no longer than three inches. the following pins are also used by the ez-ice: br bg reset gnd the ez-ice uses the ee (emulator enable) signal to take control of the AD73522 in the target system. this causes the processor to use its ereset, ebr and ebg pins instead of the reset, br and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the ribbon cable is 10 inches in length with one end fixed to the ez-ice. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board.
AD73522 C34C rev. prc 05/99 preliminary technical data preliminary technical data target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 21. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector. 3 12 34 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 21. target board connector for ez-ice the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tionyou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 x 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez- ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie and samtec. target memory interface for your target system to be compatible with the ez-ice emulator, it must comply with the memory interface guidelines listed below. pm, dm, bm, iom and cm design your program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom) and composite memory (cm) external interfaces to comply with worst case device timing requirements and switching characteristics as specified in the dsps data sheet. the performance of the ez-ice may approach published worst case specification for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst case chip specifi- cation for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. de- pending on the severity of the specification violation, you may have trouble manufacturing your system as dsp components statistically vary in switching characteristic and timing require- ments within published limits. restriction: all memory strobe signals on the AD73522 ( rd , wr , pms , dms , bms , cms and ioms ) used in your target system must have 10 k w pull-up resistors connected when the ez-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals changes. design your system to be com- patible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the reset signal. ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emula- tor space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsps external memory bus only if bus grant (bg) is asserted by the ez-ice boards dsp.
AD73522 C35C rev. prc 05/99 preliminary technical data preliminary technical data flash memory description the AD73522 features a 64k x 8 cmos page mode eeprom which can be written with a 3.0-volt-only power supply. internal erase/program is transparent to the user. featuring high performance page write, the AD73522s flash memory provides a typical byte-write time of 39 sec. the entire memory, i.e., 64k bytes, can be written page by page in as little as 2.5 seconds, when using interface features such as toggle bit or data polling to indicate the completion of a write cycle. to protect against inadvertent write, the AD73522 has on-chip hardware and software data protection schemes. the AD73522s flash memory has a guaranteed page-write endurance of 10 4 or 10 3 cycles. data retention is rated at greater than 100 years. the AD73522 is suited for applications that require convenient and economical updating of program, configuration, or data memory. flash memory connection the flash memory section of the AD73522 is configured on the byte-wide dma bus (bdma) of the dsp section as shown in figure 22. hence if boot operation is required from the AD73522s internal flash memory, the boot mode selection pins mode a, mode b and mode c should be set to zero (0). data [0-7] ce byte memory -flash 64 kbytes d 15 d 17 a 13 bms AD73522 wr rd d 8 a 0 d 16 address [0-13] address [14-15] db 7 db 0 a 13 a 0 a 15 a 14 oe we dsp section figure 22. flash interface to dsp section device operation the AD73522s page mode eeprom offers in-circuit electrical write capability. the AD73522 does not require separate erase and program operations. the internally timed write cycle executes both erase and program transparently to the user. the AD73522 has industry standard optional software data protection, which is recommended to be always enabled. read the read operation of the AD73522 is controlled by bms and rd , both have to be low for the dsp section to obtain data from the flash section. bms is used for device selection. when bms is high, the flash memory is deselected and only standby power is consumed. rd is the output control and is used to gate data from the flash output pins. the data bus is in high impedance state when either bms or rd is high. refer to the read cycle timing diagram (figure 24) for further details. write the write operation consists of three steps. the first step is the optional three byte load sequence for software data protection. this is an optional first step in the write operation, but highly recommended to ensure proper data integrity. step 2 is the byte-load cycle to a page buffer of the flash. step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. during the byte-load cycle, the addresses are latched by the falling edge of either bms or wr , whichever occurs last. the data is latched by the rising edge of either bms or wr , whichever occurs first. the internal write cycle is initiated by a timer after the rising edge of wr or bms , whichever occurs first. the write cycle, once initiated, will continue to completion, typically within 5 ms. see figures 25 and 26 for wr and bms controlled page write cycle timing diagrams. the write operation has three functional cycles: the optional software data protection load sequence, the page load cycle and the internal write cycle. the software data protection consists of a specific three byte load sequence that will leave the AD73522 protected at the end of the page write. the page load cycle consists of loading 1 to 128 bytes of data into the page buffer. the internal write cycle consists of the tblco timeout and the write timer operation. during the write operation, the only valid reads are data polling and toggle bit. the page-write operation allows the loading of up to 128 bytes of data into the page buffer of the AD73522 flash before the initiation of the internal write cycle. during the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. hence, the control logic a 15 - a 0 ce (bms) oe (rd) we (wr) db 7 - db 0 524288 bit eeprom cell array y- decoder and page latches i/o buffers and data latches address buffer & latches x- decoder figure 23. flash memory organisation
AD73522 C36C rev. prc 05/99 preliminary technical data preliminary technical data page-write feature of AD73522 allows the entire memory to be written in as little as 2.5 seconds. during the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. in each page-write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e., a7 through a15. any byte not loaded with user data will be written to ff. see figures 25 and 26 for the page-write cycle timing diagrams. if after the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (tblc) of 100 s, the AD73522 will stay in the page load cycle. additional bytes are then loaded consecutively. the page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (tblco) from the last byte-load cycle, i.e., no subsequent wr or bms high-to-low transition after the last rising edge of wr or bms . data in the page buffer can be changed by a subsequent byte-load cycle. the page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. the page to be loaded is determined by the page address of the last byte loaded. software chip-erase the AD73522 provides a flash-erase operation, which allows the user to simultaneously clear the entire flash-memory array to the 1 state. this is useful when the entire flash memory must be quickly erased. the software flash-erase operation is initiated by using a specific six byte-load sequence. after the load sequence, the device enters into an internally timed cycle similar to the write cycle. during the erase operation, the only valid read is toggle bit. see figure 30 for timing diagram. write operation status detection the AD73522 provides two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data polling (dq7) and toggle bit (dq6). the end of write detection mode is enabled after the rising we or ce whichever occurs first, which initiates the internal write cycle. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq7 or dq6. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data polling (dq7) when the AD73522 is in the internal write cycle, any attempt to read dq7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. once the write cycle is completed, dq7 will show true data. the device is then ready for the next operation. see figure 27 for data polling timing diagram. toggle bit (dq6) during the internal write cycle, any consecutive attempts to read dq6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the write cycle is completed, the toggling will stop. the device is then ready for the next operation. see figure 28 for toggle bit timing diagram. the initial read of the toggle bit will be a 1. data protection the AD73522 provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a wr or bms pulse of less than 5 ns will not initiate a write cycle. vdd power up/down detection: the write operation is inhibited when vdd is less than 2.5v. write inhibit mode: forcing rd low, bms high, or wr high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) the AD73522 flash-memory provides the jedec approved optional software data protection scheme for all data alteration operations, i.e., write and chip erase. with this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. the three byte-load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power- down. the AD73522 is shipped with the software data protection disabled. the software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (figures 25 and 26). the device will then be automatically set into the data protect mode. any subsequent write operation will require the preceding three- byte sequence. see figures 25 and 26 for the timing diagrams. to set the device into the unprotected mode, a six- byte sequence is required. see figure 29 for the timing diagram. if a write is attempted while sdp is enabled the device will be in a non-accessible state for ~ 300 s. it is recommended that software data protection always be enabled. the AD73522 software data protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). therefore using sdp for a single page write will enable sdp for the entire array. single pages by themselves cannot be sdp enabled or disabled. single power supply reprogrammable nonvolatile memories may be unintentionally altered. sst strongly recommends that software data protection (sdp) always be enabled. the AD73522 should be programmed using the sdp command sequence. it is recommended that the sdp disable command sequence not be issued to the device prior to writing.
AD73522 C37C rev. prc 05/99 preliminary technical data preliminary technical data address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 high-z v ih address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 figure 24. read cycle timing figure 25. wr controlled page mode write cycle timing
AD73522 C38C rev. prc 05/99 preliminary technical data preliminary technical data address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 figure 26. bms controlled page mode write cycle timing address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 figure 27. data\ polling timing
AD73522 C39C rev. prc 05/99 preliminary technical data preliminary technical data address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 figure 28. toggle bit timing address a 15-0 ce (bms) we (wr) oe (rd) db 7-0 figure 29. software data protection disable timing
AD73522 C40C rev. prc 05/99 preliminary technical data preliminary technical data figure 30. software flash-memory erase timing address a 15-0 ce (bms) we (wr) oe (rd) db 7-0
AD73522 C41C rev. prc 05/99 preliminary technical data preliminary technical data analog front end (afe) interfacing the afe section of the AD73522 features two voiceband input/output channels, each with 16-bit linear resolution. connectivity to the afe section from the dsp is uncommitted thus allowing the user the flexibility of connecting in the mode or configuration of their choice. this section will detail several configurations - with no extra afe channels configured and with two extra afe channels configured (using an external ad73322 dual afe). dsp sport to afe interfacing the sclk, sdo, sdofs, sdi and sdifs pins of sport2 must be connected to the serial clock, receive data, receive data frame sync, transmit data and transmit data frame sync pins respectively of either sport0 or sport1.. the se pin may be controlled from a parallel output pin or flag pin such as fl0-2 or, where sport2 powerdown is not required, it can be permanently strapped high using a suitable pull-up resistor. the resetc pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. in the event of tying it to the global system reset, it is advisable to operate the device in mixed mode, which allows a software reset, otherwise there is no convenient way of resetting the afe section. tfs dt sclk dr rfs dsp section afe section sdifs sdi sclk sdo sdofs fl0 fl1 resetc se figure 21. AD73522 afe to dsp connection cascade operation where it is required to configure extra analog i/o channels to the existing two channels on the AD73522, it is possible to cascade up to 6 more channels (using single channel ad73311 or dual channel ad73322 afes) by using the scheme described in figure 23. it is necessary however to ensure that the timing of the se and reset signals is syn- chronized at each device in the cascade. a simple d type flip flop is sufficient to sync each signal to the master clock mclk, as in figure 22. 1/2 74hc74 clk dq dsp control to se mclk se signal synchronized to mclk 1/2 74hc74 clk dq dsp control to reset mclk reset signal synchronized to mclk figure 22. se and reset sync circuit for cascaded operation connection of a cascade of devices to a dsp, as shown in figure 23, is no more complicated than connecting a single device. instead of connecting the sdo and sdofs to the dsps rx port, these are now daisy-chained to the sdi and sdifs of the next device in the cascade. the sdo and sdofs of the final device in the cascade are connected to the dsp sections rx port to complete the cascade. se and reset on all devices are fed from the signals that were synchronized with the mclk using the circuit as described above. the sclk from only one device need be connected to the dsp sections sclk input(s) as all devices will be running at the same sclk frequency and phase. tfs dt dr rfs afe section sdifs sdi sclk sdo sdofs sclk device 1 mclk se reset additional ad73322 codec sdifs sdi sclk sdo sdofs device 2 mclk se reset 74hc74 q1 q2 d1 d2 fl0 fl1 dsp section figure 23. connection of an ad73322 cascaded to AD73522 interfacing to the afes analog inputs and outputs the afe section of the AD73522 offers a flexible interface for microphone pickups, line level signals or pstn line intefaces. this section will detail some of the configurations that can be used with the input and output sections. the ad73322 features both differential inputs and outputs on each channel to provide optimal performance and avoid common mode noise. it is also possible to interface either inputs or outputs in single-ended mode. this section details the choice of input and output configurations and also gives some tips towards successful configuration of the analog interface sections.
AD73522 C42C rev. prc 05/99 preliminary technical data preliminary technical data vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn 1 vinp1 vfbp1 voutp1 voutn1 refout reference v ref anti-alias filter 0.047 m f 100 v 0.047 m f 100 v refcap 0.1 m f 0/38db pga figure 24. analog input (dc-coupled) analog inputs there are several different ways in which the analog input (encoder) section of the AD73522 can be interfaced to external circuitry. it provides optional input amplifiers which allows sources with high source impedance to drive the adc section correctly. when the input amplifiers are enabled, the input channel is configured as a differential pair of inverting amplifiers referenced to the internal reference (refcap) level. the inverting terminals of the input amplifier pair are designated as pins vinp1 and vinn1 for channel 1 (vinp2 and vinn2 for channel 2) and the amplifier feedback connections are available on pins vfbp1 and vfbn1 for channel 1 (vfbp2 and vfbn2 for channel 2). for applications where external signal buffering is required, the input amplifiers can be bypassed and the adc driven directly. w hen the input amplifiers are disabled, the sigma- delta modulators input section (sc pga) is accessed directly through the vfbp1 and vfbn1 pins for channel 1 (vfbp2 and vfbn2 for channel 2). it is also possible to drive the adcs in either differential or single-ended modes. if the single-ended mode is chosen it is possible using software control to multiplex between two single-ended inputs connected to the positive and negative input pins. the primary concerns in interfacing to the adc are firstly to provide adequate anti-alias filtering and to ensure that the signal so urce will drive the switched-capacitor input of the adc co rrectly. the sigma-delta design of the adc and its over sampling characteristics simplify the antialias requirements but it must be remembered that the single pole rc filter is primarily intended to eliminate aliasing of frequencies above the nyquist frequency of the sigma-delta modulators sampling rate (typically 2.048 mhz). it may still require a more specific digital filter implementation in the dsp to provide the final signal frequency response characteristics. it is recommended that for optimum performance that the capacitors used for the antialiasing filter be of high quality dielectric (npo). the second issue mentioned above is interfacing the signal source to the adcs switched capacitor input load. the sc input presents a complex dynamic load to a signal source, therefore, it is important to understand that the slew rate characteristic is an important consideration when choosing external buffers for use with the AD73522. the internal inverting op amps on the AD73522s afe are specifically designed to interface to the adcs sc input stage. the AD73522s on-chip 38 db preamplifier can be enabled when there is not enough gain in the input circuit; the pream- plifier is configured by bits igs0-2 of crd. the total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the adc that does not exceed the maximum input range. the dc biasing of the analog input signal is accomplished with an on-chip voltage reference. if the input signal is not biased at the in ternal reference level (via refout), then it must be ac-coupled with external co upling capacitors. c in should be 0.1 f or larger. the dc biasing of the input can then be accomplished using resistors to refout as in figures 31 and 32. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn 1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference 0/38db pga v ref optional buffer anti-alias filter 0.1 m f 100 v 100 v 0.047 m f 0.047 m f figure 25. analog input (dc-coupled) using external amplifiers the ad73322s adc inputs are biased about the internal reference level (refcap level), therefore it may be necessary to either bias external signals to this level using the buffered re fout level as the reference. this is applicable in either dc- or ac-coupled configurations. in the case of dc coupling, the signal (biased to refout) may be applied directly to the inputs (using amplifier bypass), as shown in figure 24, or it may be conditioned in an external op amp where it can also be biased to the reference level using the buffered refout signal as shown in figure 25 or it is possible to connect inputs directly to the AD73522s input op amps as shown in figure 26.
AD73522 C43C rev. prc 05/99 preliminary technical data preliminary technical data vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refout reference v ref 50k v 100pf 50k v 100pf 50k v 50k v refcap 0.1 m f 0/38db pga figure 26. analog input (dc-coupled) using internal amplifiers in the case of ac coupling, a capacitor is used to couple the signal to the input of the adc. the adc input must be biased to the internal reference (refcap) level which is done by connecting the input to the refout pin through a 10 k w resistor as shown in figure 27. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn 1 vinp1 vfbp1 voutp1 voutn1 refout reference 0/38db pga v ref 0.047 m f 0.047 m f 100 v 100 v 10k v 0.1 m f 0.1 m f refcap 0.1 m f 10k v figure 27. analog input (ac-coupled) differential if the adc is being connected in single-ended mode, the AD73522 s hould be programmed for single-ended mode using the seen and inv bits of crf and the inputs con- nected as shown in figure 28. when operated in single- ended input mode, the AD73522 can multiplex one of the two inputs to the adc input. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn 1 vinp1 vfbp1 voutp1 voutn1 refout reference 0/38db pga v ref 0.047 m f 100 v 10k v 0.1 m f refcap 0.1 m f figure 28. analog input (ac-coupled) single-ended if best performance is required from a single-ended source, it is possible to configure the AD73522s input amplifiers as a single-ended to differential converter as shown in figure 29. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn 1 vinp1 vfbp1 voutp1 voutn1 refout reference 0/38db pga 50k v 100pf 50k v 100pf 50k v 50k v refcap 0.1 m f v ref figure 29. single-ended to differential conversion on analog input interfacing to an electret microphone figure 30 details an interface for an electret microphone which may be used in some voice applications. electret microphones typically feature a fet amplifier whose output is accessed on the same lead which supplies power to the microphone, therefore this output signal must be capacitively coupled to remove the power supply (dc) component. in this circuit the AD73522 input channel is being used in single- ended mode where the internal inverting amplifier provides suitable gain to scale the input signal relative to the adcs full-scale input range. the buffered internal reference level at refout is used via an external buffer to provide power to the electret microphone. this provides a quiet, stable supply for the microphone. if this is not a concern, then the microphone can be powered from the system power supply.
AD73522 C44C rev. prc 05/99 preliminary technical data preliminary technical data vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference v ref 0/38db pga electret probe 10 m f r a r b r1 r2 +5v c2 c1 c refcap figure 30. electret microphone interface circuit analog output the AD73522s differential analog output (vout) is produced by an on-chip differential amplifier. the differential output can be ac-coupled or dc-coupled directly to a load which can be a headset or the input of an external amplifier (the specified minimum resistive load on the output section is 150 w .) it is possible to connect the outputs in either a differential or a single-ended configuration but please note that the effective maximum output voltage swing (peak to peak) is halved in the case of single-ended connection. figure 31 shows a simple circuit providing a differential output with ac coupling. the capacitors in this circuit (c out ) are optional; if used, their value can be chosen as follows: c out = 1 2 p f c r load where f c = desired cutoff frequency. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference c refcap r load c out c out figure 31. example circuit for differential output figure 32 shows an example circuit for providing a single- ended output with ac coupling. the capacitor of this circuit (c out ) is not optional if dc current drain is to be avoided. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference r load c out 0.1 m f figure 32. example circuit for single-ended output differential to single-ended output in some applications it may be desireable to convert the full differential output of the decoder channel to a single-ended signal. the circuit of figure 33 shows a scheme for doing this. vfbn1 gain 6 1 +6/15db pga continuous time low-pass filter v ref vinn1 vinp1 vfbp1 voutp1 voutn1 refcap refout reference v ref 0/38db pga r load r i r i r f r f 0.1 m f figure 33. example circuit for differential to single- ended output conversion
AD73522 C45C rev. prc 05/99 preliminary technical data preliminary technical data
AD73522 C46C rev. prc 05/99 printed in u.s.a. 00000000 outline dimensions dimensions shown in inches and (mm). preliminary technical data preliminary technical data 119-ball plastic ball grid array (pbga) b-119 a b c d e f g h j k l m n p r t u 7 65 4 3 2 1 0.050 (1.27) bsc 0.800 (20.32) bsc 0.300 (7.62) bsc 0.050 (1.27) bsc 0.126 (3.19) ref 0.033 (0.84) ref bottom view a1 top view 0.866 (22.00) 0.858 (21.80) 0.559 (14.20) 0.543 (13.80) 0.089 (2.27) 0.073 (1.85) detail a seating plane 0.037 (0.95) 0.033 (0.85) 0.028 (0.70) 0.020 (0.50) detail a 0.035 (0.90) 0.024 (0.60) ball diameter 0.022 (0.56) ref

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